geopm_pio_msr(7) – Signals and controls for Model Specific Registers (MSRs)
Description
The MSR IOGroup implements the geopm::IOGroup(3) interface to provide hardware signals and controls for Model Specific Registers (MSRs).
Configuration
The set of signals and controls supported by the MSR IOGroup is configurable, as the MSRs that are available depend on the architecture and the particular CPU. The MSR IOGroup will declare a set of common signals and controls, including MSRs for CPU performance, temperature and power.
Additional MSRs can be specified via configuration files. If the
GEOPM_MSR_CONFIG_PATH environment variable is set, the paths specified there
will be checked for any JSON files prefixed with msr_. The /etc/geopm
directory will also be searched. The files must follow this schema:
{
"$schema": "http://json-schema.org/draft-04/schema#",
"id": "https://geopm.github.io/msrs.schema.json",
"title": "MSR specification",
"definitions" : {
"msrFields": {
"type": "object",
"properties": {
"begin_bit": {
"type": "integer"
},
"end_bit": {
"type": "integer"
},
"function": {
"enum": ["scale", "log_half", "7_bit_float", "overflow", "logic"]
},
"units": {
"enum": ["none", "seconds", "hertz", "watts", "joules", "celsius"]
},
"scalar": {
"type": "number"
},
"behavior": {
"enum": ["constant", "monotone", "variable", "label"]
},
"writeable": {
"type": "boolean"
},
"aggregation": {
"enum": ["sum", "average", "median", "logical_and", "logical_or", "region_hash", "region_hint", "min", "max", "stddev", "select_first", "expect_same"]
},
"description": {
"type": "string"
}
},
"required": ["begin_bit", "end_bit", "function", "scalar", "units", "writeable", "behavior", "aggregation"],
"additionalProperties": false
},
"msrObject": {
"type": "object",
"properties": {
"offset": {
"type": "string"
},
"domain": {
"enum": ["board", "package", "core", "cpu", "memory", "package_integrated_memory", "nic", "package_integrated_nic", "gpu", "package_integrated_gpu", "gpu_chip"]
},
"fields": {
"type": "object",
"additionalProperties": {
"$ref": "#/definitions/msrFields"
}
}
},
"required": ["offset", "domain", "fields"],
"additionalProperties": false
}
},
"type": "object",
"properties": {
"msrs": {
"type": "object",
"additionalProperties": {
"$ref": "#/definitions/msrObject"
}
}
},
"additionalProperties": false
}
For an example of an MSR configuration file, please see: <msr_reasons.json>
Note
Before GEOPM 3.0, MSR configuration files were stored near the GEOPM
library objects (e.g., in /usr/lib64/geopm), and discovered in the
search paths from the GEOPM_PLUGIN_PATH environment variable. Since
version 3.0, GEOPM additionally searches /etc/geopm and locations from
the GEOPM_MSR_CONFIG_PATH environment variable. Future releases may
stop searching the library and plugin paths for MSR configuration data.
If GEOPM uses a configuration from the old location, then a deprecation
warning is emitted.
This guide includes a list of signals and controls that are more commonly available. Use geopmread and geopmwrite to query the full set of signals and controls that are available on a particular system.
Concurrent Access
Usage and access to most MSRs is restricted to ring 0. However, there is no hardware mechanism available to reserve access to MSRs, so access is on a first-come-first-served basis. As a result, it’s possible for a process to overwrite previously programmed settings by another process. So care must be taken when using GEOPM with other tools that might also access and configure MSRs (e.g. a Virtual Machine Monitor or a performance monitoring tool) to avoid concurrent access and unexpected results.
Please consult the following for further information and guidelines for sharing access to MSRs: Performance Monitoring Unit Sharing Guide (Intel white paper).
Signals
Some MSR signals are available on specific miroarchitectures. Architectural signals are available across Intel x86 microarchitectures.
Architectural Signals
MSR::TIME_STAMP_COUNTER:TIMESTAMP_COUNTAn always running, monotonically increasing counter that is incremented at a constant rate. For use as a wall clock timer.
Aggregation: select_first
Domain: cpu
Format: integer
Unit: none
MSR::MPERF:MCNTA counter incrementing at the processor’s base, maximum performance frequency. This counter cannot measure processor performance when the CPU is inactive.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::APERF:ACNTA counter incrementing at the processor’s actual frequency. This counter cannot measure processor performance when the CPU is inactive.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::THERM_INTERRUPT:THRESH_1The temperature at or above which the MSR::THERM_STATUS:THERMAL_THRESH_1_STATUS indicator is set, in degrees below MSR::TEMPERATURE_TARGET:PROCHOT_MIN.
Aggregation: expect_same
Domain: core
Format: integer
Unit: celsius
MSR::THERM_INTERRUPT:THRESH_2The temperature at or above which the MSR::THERM_STATUS:THERMAL_THRESH_2_STATUS indicator is set, in degrees below MSR::TEMPERATURE_TARGET:PROCHOT_MIN.
Aggregation: expect_same
Domain: core
Format: integer
Unit: celsius
MSR::THERM_STATUS:THERMAL_STATUS_FLAGIndicates whether the core’s on-die sensor reads a high temperature (PROCHOT). When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: core
Format: integer
Unit: none
MSR::THERM_STATUS:PROCHOT_EVENTIndicates whether a high temperature (PROCHOT) or forced power reduction (FORCEPR) is being externally asserted. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: core
Format: integer
Unit: none
MSR::THERM_STATUS:CRITICAL_TEMP_STATUSIndicates whether the core’s on-die sensor reads a critical temperature and the system cannot guarantee reliable operation. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: core
Format: integer
Unit: none
MSR::THERM_STATUS:THERMAL_THRESH_1_STATUSIndicates whether the core’s on-die sensor reads equal to or hotter than the threshold in MSR::THERM_INTERRUPT:THRESH_1. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: core
Format: integer
Unit: none
MSR::THERM_STATUS:THERMAL_THRESH_2_STATUSIndicates whether the core’s on-die sensor reads equal to or hotter than the threshold in MSR::THERM_INTERRUPT:THRESH_2. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: core
Format: integer
Unit: none
MSR::THERM_STATUS:POWER_LIMIT_STATUSIndicates whether requested P-States or requested clock duty cycles are not met. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: core
Format: integer
Unit: none
MSR::THERM_STATUS:DIGITAL_READOUTThe temperature reading on this core’s on-die sensor, in degrees below MSR::TEMPERATURE_TARGET:PROCHOT_MIN.
Aggregation: average
Domain: core
Format: integer
Unit: celsius
MSR::THERM_STATUS:RESOLUTIONThe resolution of the sensor that measures MSR::THERM_STATUS:DIGITAL_READOUT temperature.
Aggregation: expect_same
Domain: core
Format: integer
Unit: celsius
MSR::THERM_STATUS:READING_VALIDIndicates whether MSR::THERM_STATUS:DIGITAL_READOUT contains a valid temperature readout. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: core
Format: integer
Unit: none
MSR::MISC_ENABLE:LIMIT_CPUID_MAXVALIndicates whether the operating system does not support usage of the CPUID instruction with functions that require EAX values great than 2. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PACKAGE_THERM_INTERRUPT:THRESH_1The temperature at or above which the MSR::THERM_STATUS:THERMAL_THRESH_1_STATUS indicator is set, in degrees below MSR::TEMPERATURE_TARGET:PROCHOT_MIN.
Aggregation: expect_same
Domain: package
Format: integer
Unit: celsius
MSR::PACKAGE_THERM_INTERRUPT:THRESH_2The temperature at or above which the MSR::THERM_STATUS:THERMAL_THRESH_2_STATUS indicator is set, in degrees below MSR::TEMPERATURE_TARGET:PROCHOT_MIN.
Aggregation: expect_same
Domain: package
Format: integer
Unit: celsius
MSR::PACKAGE_THERM_STATUS:THERMAL_STATUS_FLAGIndicates whether the package’s on-die sensor reads a high temperature (PROCHOT). When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PACKAGE_THERM_STATUS:PROCHOT_EVENTIndicates whether a package high temperature (PROCHOT) or forced power reduction (FORCEPR) is being externally asserted. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PACKAGE_THERM_STATUS:CRITICAL_TEMP_STATUSIndicates whether the package’s on-die sensor reads a critical temperature and the system cannot guarantee reliable operation. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PACKAGE_THERM_STATUS:THERMAL_THRESH_1_STATUSIndicates whether the package’s on-die sensor reads equal to or hotter than the threshold in MSR::PACKAGE_THERM_INTERRUPT:THRESH_1. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PACKAGE_THERM_STATUS:THERMAL_THRESH_2_STATUSIndicates whether the package’s on-die sensor reads equal to or hotter than the threshold in MSR::PACKAGE_THERM_INTERRUPT:THRESH_2. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PACKAGE_THERM_STATUS:POWER_LIMIT_STATUSIndicates whether requested P-States or requested clock duty cycles are not met due to a package power limit. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PACKAGE_THERM_STATUS:DIGITAL_READOUTThe temperature reading on this package’s on-die sensor, in degrees below MSR::TEMPERATURE_TARGET:PROCHOT_MIN.
Aggregation: average
Domain: package
Format: integer
Unit: celsius
MSR::IA32_PMC0:PERFCTRThe count of events detected by MSR::IA32_PERFEVTSEL0.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PMC1:PERFCTRThe count of events detected by MSR::IA32_PERFEVTSEL1.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PMC2:PERFCTRThe count of events detected by MSR::IA32_PERFEVTSEL2.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PMC3:PERFCTRThe count of events detected by MSR::IA32_PERFEVTSEL3.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::FIXED_CTR0:INST_RETIRED_ANYThe count of the number of instructions executed.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::FIXED_CTR1:CPU_CLK_UNHALTED_THREADThe count of the number of cycles while the logical processor is not in a halt state. The count rate may change based on core frequency.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::FIXED_CTR2:CPU_CLK_UNHALTED_REF_TSCThe count of the number of cycles while the logical processor is not in a halt state and not in a stop-clock state. The count rate is fixed at the TIMESTAMP_COUNT rate.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
Knights Landing (KNL) Signals
MSR::PLATFORM_INFO:MAX_NON_TURBO_RATIOThe processor’s maximum non-turbo frequency.
Aggregation: average
Domain: package
Format: integer
Unit: hertz
MSR::PLATFORM_INFO:PROGRAMMABLE_RATIO_LIMITS_TURBO_MODEIndicates whether the MSR::TURBO_RATIO_LIMIT:* signals are also available as controls. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PLATFORM_INFO:PROGRAMMABLE_TDP_LIMITS_TURBO_MODEIndicates whether this platform supports programmable TDP limits for turbo mode. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PLATFORM_INFO:MAX_EFFICIENCY_RATIOThe minimum operating frequency of the processor.
Aggregation: average
Domain: package
Format: integer
Unit: hertz
MSR::PERF_STATUS:FREQThe current operating frequency of the CPU.
Aggregation: average
Domain: package
Format: integer
Unit: hertz
MSR::TEMPERATURE_TARGET:PROCHOT_MINThe lowest temperature considered a high temperature. Measured temperatures at or above this value will generate a PROCHOT event.
Aggregation: expect_same
Domain: core
Format: integer
Unit: celsius
MSR::TEMPERATURE_TARGET:TCC_ACTIVE_OFFSETAn offset to subtract from MSR::TEMPERATURE_TARGET:PROCHOT_MIN as the cutoff to generate a PROCHOT event.
Aggregation: expect_same
Domain: core
Format: integer
Unit: celsius
MSR::TURBO_RATIO_LIMIT:GROUP_0_MAX_CORESDefines the group 0 active core count, which is the number of active cores for a maximum turbo frequency of MSR::TURBO_RATIO_LIMIT:GROUP_0_MAX_RATIO_LIMIT.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::TURBO_RATIO_LIMIT:GROUP_0_MAX_RATIO_LIMITMaximum turbo frequency with up to the group 0 active core count.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:GROUP_1_INCREMENTAL_CORESAdditional active cores to define the group 1 active core count, beyond the group 0 active core count.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::TURBO_RATIO_LIMIT:GROUP_1_RATIO_LIMIT_DELTADrop in maximum turbo frequency for the group 1 active core count, relative to the group 0 maximum turbo frequency.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:GROUP_2_INCREMENTAL_CORESAdditional active cores to define the group 2 active core count, beyond the group 1 active core count.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::TURBO_RATIO_LIMIT:GROUP_2_RATIO_LIMIT_DELTADrop in maximum turbo frequency for the group 2 active core count, relative to the group 1 maximum turbo frequency.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:GROUP_3_INCREMENTAL_CORESAdditional active cores to define the group 3 active core count, beyond the group 2 active core count.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::TURBO_RATIO_LIMIT:GROUP_3_RATIO_LIMIT_DELTADrop in maximum turbo frequency for the group 3 active core count, relative to the group 2 maximum turbo frequency.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:GROUP_4_INCREMENTAL_CORESAdditional active cores to define the group 4 active core count, beyond the group 3 active core count.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::TURBO_RATIO_LIMIT:GROUP_4_RATIO_LIMIT_DELTADrop in maximum turbo frequency for the group 4 active core count, relative to the group 3 maximum turbo frequency.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:GROUP_5_INCREMENTAL_CORESAdditional active cores to define the group 5 active core count, beyond the group 4 active core count.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::TURBO_RATIO_LIMIT:GROUP_5_RATIO_LIMIT_DELTADrop in maximum turbo frequency for the group 5 active core count, relative to the group 4 maximum turbo frequency.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:GROUP_6_INCREMENTAL_CORESAdditional active cores to define the group 6 active core count, beyond the group 5 active core count.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::TURBO_RATIO_LIMIT:GROUP_6_RATIO_LIMIT_DELTADrop in maximum turbo frequency for the group 6 active core count, relative to the group 5 maximum turbo frequency.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::RAPL_POWER_UNIT:POWERThe resolution of RAPL power interfaces.
Aggregation: expect_same
Domain: package
Format: integer
Unit: watts
MSR::RAPL_POWER_UNIT:ENERGYThe resolution of RAPL energy interfaces.
Aggregation: expect_same
Domain: package
Format: integer
Unit: joules
MSR::RAPL_POWER_UNIT:TIMEThe resolution of RAPL time interfaces.
Aggregation: expect_same
Domain: package
Format: integer
Unit: seconds
MSR::PKG_POWER_LIMIT:LOCKIgnore any changes to PL1 and PL2 configuration in PKG_POWER_LIMIT until the next reset.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::PKG_ENERGY_STATUS:ENERGYAn increasing meter of energy consumed by the package over time. It will reset periodically due to roll-over.
Aggregation: sum
Domain: package
Format: integer
Unit: joules
MSR::PKG_POWER_INFO:THERMAL_SPEC_POWERMaximum power to stay within the thermal limits based on the design (TDP).
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_INFO:MIN_POWERThe minimum power limit based on the electrical specification.
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_INFO:MAX_POWERThe maximum power limit based on the electrical specification.
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_INFO:MAX_TIME_WINDOWThe maximum time accepted in MSR::PKG_POWER_LIMIT:PL1_TIME_WINDOW and MSR::PKG_POWER_LIMIT:PL2_TIME_WINDOW.
Aggregation: expect_same
Domain: package
Format: integer
Unit: seconds
MSR::DRAM_ENERGY_STATUS:ENERGYAn increasing meter of energy consumed by the DRAM over time. It will reset periodically due to roll-over.
Aggregation: sum
Domain: package
Format: integer
Unit: joules
MSR::DRAM_PERF_STATUS:THROTTLE_TIMEThe amount of time that the package was throttled below the requested frequency due to MSR::DRAM_POWER_LIMIT:POWER_LIMIT.
Aggregation: sum
Domain: memory
Format: integer
Unit: seconds
MSR::DRAM_POWER_INFO:THERMAL_SPEC_POWERMaximum DRAM power to stay within the thermal limits based on the design.
Aggregation: sum
Domain: memory
Format: integer
Unit: watts
MSR::DRAM_POWER_INFO:MIN_POWERThe minimum DRAM power limit based on the electrical specification.
Aggregation: sum
Domain: memory
Format: integer
Unit: watts
MSR::DRAM_POWER_INFO:MAX_POWERThe maximum DRAM power limit based on the electrical specification.
Aggregation: sum
Domain: memory
Format: integer
Unit: watts
MSR::DRAM_POWER_INFO:MAX_TIME_WINDOWThe maximum value accepted in MSR::DRAM_POWER_LIMIT:TIME_WINDOW.
Aggregation: expect_same
Domain: memory
Format: integer
Unit: seconds
MSR::UNCORE_PERF_STATUS:FREQThe current uncore frequency.
Aggregation: average
Domain: package
Format: integer
Unit: hertz
Sandy Bridge (SNB) Signals
MSR::PLATFORM_INFO:MAX_NON_TURBO_RATIOThe processor’s maximum non-turbo frequency.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::PLATFORM_INFO:PROGRAMMABLE_RATIO_LIMITS_TURBO_MODEIndicates whether the MSR::TURBO_RATIO_LIMIT:* signals are also available as controls.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::PLATFORM_INFO:PROGRAMMABLE_TDP_LIMITS_TURBO_MODEIndicates whether this platform supports programmable TDP limits for turbo mode.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::PLATFORM_INFO:MAX_EFFICIENCY_RATIOThe minimum operating frequency of the processor.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::PERF_STATUS:FREQThe current operating frequency of the CPU.
Aggregation: average
Domain: package
Format: integer
Unit: hertz
MSR::TEMPERATURE_TARGET:PROCHOT_MINThe lowest temperature considered a high temperature. Measured temperatures at or above this value will generate a PROCHOT event.
Aggregation: expect_same
Domain: core
Format: integer
Unit: celsius
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_1COREMaximum turbo frequency with up to 1 active core.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_2CORESMaximum turbo frequency with up to 2 active cores.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_3CORESMaximum turbo frequency with up to 3 active cores.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_4CORESMaximum turbo frequency with up to 4 active cores.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_5CORESMaximum turbo frequency with up to 5 active cores.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_6CORESMaximum turbo frequency with up to 6 active cores.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_7CORESMaximum turbo frequency with up to 7 active cores.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_8CORESMaximum turbo frequency with up to 8 active cores.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::RAPL_POWER_UNIT:POWERThe resolution of RAPL power interfaces.
Aggregation: expect_same
Domain: package
Format: integer
Unit: watts
MSR::RAPL_POWER_UNIT:ENERGYThe resolution of RAPL energy interfaces.
Aggregation: expect_same
Domain: package
Format: integer
Unit: joules
MSR::RAPL_POWER_UNIT:TIMEThe resolution of RAPL time interfaces.
Aggregation: expect_same
Domain: package
Format: integer
Unit: seconds
MSR::PKG_POWER_LIMIT:LOCKIgnore any changes to PL1 and PL2 configuration in PKG_POWER_LIMIT until the next reset.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::PKG_ENERGY_STATUS:ENERGYAn increasing meter of energy consumed by the package over time. It will reset periodically due to roll-over.
Aggregation: sum
Domain: package
Format: integer
Unit: joules
MSR::PKG_POWER_INFO:THERMAL_SPEC_POWERMaximum power to stay within the thermal limits based on the design (TDP).
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_INFO:MIN_POWERThe minimum power limit based on the electrical specification.
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_INFO:MAX_POWERThe maximum power limit based on the electrical specification.
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_INFO:MAX_TIME_WINDOWThe maximum time accepted in MSR::PKG_POWER_LIMIT:PL1_TIME_WINDOW and MSR::PKG_POWER_LIMIT:PL2_TIME_WINDOW.
Aggregation: expect_same
Domain: package
Format: integer
Unit: seconds
MSR::DRAM_POWER_LIMIT:LOCKIgnore any changes to configuration in DRAM_POWER_LIMIT until the next reset.
Aggregation: expect_same
Domain: memory
Format: integer
Unit: none
MSR::DRAM_ENERGY_STATUS:ENERGYAn increasing meter of energy consumed by the DRAM over time. It will reset periodically due to roll-over.
Aggregation: sum
Domain: package
Format: integer
Unit: joules
MSR::DRAM_PERF_STATUS:THROTTLE_TIMEThe amount of time that the package was throttled below the requested frequency due to MSR::DRAM_POWER_LIMIT:POWER_LIMIT.
Aggregation: sum
Domain: memory
Format: integer
Unit: seconds
MSR::DRAM_POWER_INFO:THERMAL_SPEC_POWERMaximum DRAM power to stay within the thermal limits based on the design.
Aggregation: sum
Domain: memory
Format: integer
Unit: watts
MSR::DRAM_POWER_INFO:MIN_POWERThe minimum DRAM power limit based on the electrical specification.
Aggregation: sum
Domain: memory
Format: integer
Unit: watts
MSR::DRAM_POWER_INFO:MAX_POWERThe maximum DRAM power limit based on the electrical specification.
Aggregation: sum
Domain: memory
Format: integer
Unit: watts
MSR::DRAM_POWER_INFO:MAX_TIME_WINDOWThe maximum value accepted in MSR::DRAM_POWER_LIMIT:TIME_WINDOW.
Aggregation: expect_same
Domain: memory
Format: integer
Unit: seconds
Haswell (HSX) Signals
MSR::PLATFORM_INFO:MAX_NON_TURBO_RATIOThe processor’s maximum non-turbo frequency.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::PLATFORM_INFO:PROGRAMMABLE_RATIO_LIMITS_TURBO_MODEIndicates whether the MSR::TURBO_RATIO_LIMIT:* signals are also available as controls.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::PLATFORM_INFO:PROGRAMMABLE_TDP_LIMITS_TURBO_MODEIndicates whether this platform supports programmable TDP limits for turbo mode.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::PLATFORM_INFO:PROGRAMMABLE_TCC_ACTIVATION_OFFSETIndicates whether the platform permits writes to MSR::TEMPERATURE_TARGET:TCC_ACTIVE_OFFSET.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::PLATFORM_INFO:MAX_EFFICIENCY_RATIOThe minimum operating frequency of the processor.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::PERF_STATUS:FREQThe current operating frequency of the CPU.
Aggregation: average
Domain: cpu
Format: integer
Unit: hertz
MSR::TEMPERATURE_TARGET:PROCHOT_MINThe lowest temperature considered a high temperature. Measured temperatures at or above this value will generate a PROCHOT event.
Aggregation: expect_same
Domain: core
Format: integer
Unit: celsius
MSR::TEMPERATURE_TARGET:TCC_ACTIVE_OFFSETAn offset to subtract from MSR::TEMPERATURE_TARGET:PROCHOT_MIN as the cutoff to generate a PROCHOT event.
Aggregation: expect_same
Domain: core
Format: integer
Unit: celsius
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_1COREMaximum turbo frequency when 1 core is active.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_2CORESMaximum turbo frequency when 2 cores are active.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_3CORESMaximum turbo frequency when 3 cores are active.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_4CORESMaximum turbo frequency when 4 cores are active.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_5CORESMaximum turbo frequency when 5 cores are active.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_6CORESMaximum turbo frequency when 6 cores are active.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_7CORESMaximum turbo frequency when 7 cores are active.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_8CORESMaximum turbo frequency when 8 cores are active.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT1:MAX_RATIO_LIMIT_9CORESMaximum turbo frequency when 9 cores are active.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT1:MAX_RATIO_LIMIT_10CORESMaximum turbo frequency when 10 cores are active.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT1:MAX_RATIO_LIMIT_11CORESMaximum turbo frequency when 11 cores are active.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT1:MAX_RATIO_LIMIT_12CORESMaximum turbo frequency when 12 cores are active.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT1:MAX_RATIO_LIMIT_13CORESMaximum turbo frequency when 13 cores are active.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT1:MAX_RATIO_LIMIT_14CORESMaximum turbo frequency when 14 cores are active.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT1:MAX_RATIO_LIMIT_15CORESMaximum turbo frequency when 15 cores are active.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT1:MAX_RATIO_LIMIT_16CORESMaximum turbo frequency when 16 cores are active.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT2:MAX_RATIO_LIMIT_17CORESMaximum turbo frequency when 17 cores are active.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT2:MAX_RATIO_LIMIT_18CORESMaximum turbo frequency when 18 cores are active.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::RAPL_POWER_UNIT:POWERThe resolution of RAPL power interfaces.
Aggregation: expect_same
Domain: package
Format: integer
Unit: watts
MSR::RAPL_POWER_UNIT:ENERGYThe resolution of RAPL energy interfaces.
Aggregation: expect_same
Domain: package
Format: integer
Unit: joules
MSR::RAPL_POWER_UNIT:TIMEThe resolution of RAPL time interfaces.
Aggregation: expect_same
Domain: package
Format: integer
Unit: seconds
MSR::PKG_POWER_LIMIT:LOCKIgnore any changes to PL1 and PL2 configuration in PKG_POWER_LIMIT until the next reset.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::PKG_ENERGY_STATUS:ENERGYAn increasing meter of energy consumed by the package over time. It will reset periodically due to roll-over.
Aggregation: sum
Domain: package
Format: integer
Unit: joules
MSR::PKG_POWER_INFO:THERMAL_SPEC_POWERMaximum power to stay within the thermal limits based on the design (TDP).
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_INFO:MIN_POWERThe minimum power limit based on the electrical specification.
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_INFO:MAX_POWERThe maximum power limit based on the electrical specification.
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_INFO:MAX_TIME_WINDOWThe maximum time accepted in MSR::PKG_POWER_LIMIT:PL1_TIME_WINDOW and MSR::PKG_POWER_LIMIT:PL2_TIME_WINDOW.
Aggregation: expect_same
Domain: package
Format: integer
Unit: seconds
MSR::DRAM_POWER_LIMIT:LOCKIgnore any changes to configuration in DRAM_POWER_LIMIT until the next reset.
Aggregation: expect_same
Domain: memory
Format: integer
Unit: none
MSR::DRAM_ENERGY_STATUS:ENERGYAn increasing meter of energy consumed by the DRAM over time. It will reset periodically due to roll-over.
Aggregation: sum
Domain: package
Format: integer
Unit: joules
MSR::DRAM_PERF_STATUS:THROTTLE_TIMEThe amount of time that the package was throttled below the requested frequency due to MSR::DRAM_POWER_LIMIT:POWER_LIMIT.
Aggregation: sum
Domain: memory
Format: integer
Unit: seconds
MSR::DRAM_POWER_INFO:THERMAL_SPEC_POWERMaximum DRAM power to stay within the thermal limits based on the design.
Aggregation: sum
Domain: memory
Format: integer
Unit: watts
MSR::DRAM_POWER_INFO:MIN_POWERThe minimum DRAM power limit based on the electrical specification.
Aggregation: sum
Domain: memory
Format: integer
Unit: watts
MSR::DRAM_POWER_INFO:MAX_POWERThe maximum DRAM power limit based on the electrical specification.
Aggregation: sum
Domain: memory
Format: integer
Unit: watts
MSR::DRAM_POWER_INFO:MAX_TIME_WINDOWThe maximum value accepted in MSR::DRAM_POWER_LIMIT:TIME_WINDOW.
Aggregation: expect_same
Domain: memory
Format: integer
Unit: seconds
MSR::UNCORE_PERF_STATUS:FREQThe current uncore frequency.
Aggregation: average
Domain: package
Format: integer
Unit: hertz
Skylake (SKX) Signals
MSR::PLATFORM_INFO:MAX_NON_TURBO_RATIOThe processor’s maximum non-turbo frequency.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::PLATFORM_INFO:PROGRAMMABLE_RATIO_LIMITS_TURBO_MODEIndicates whether the MSR::TURBO_RATIO_LIMIT:* signals are also available as controls.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::PLATFORM_INFO:PROGRAMMABLE_TDP_LIMITS_TURBO_MODEIndicates whether this platform supports programmable TDP limits for turbo mode.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::PLATFORM_INFO:PROGRAMMABLE_TCC_ACTIVATION_OFFSETIndicates whether the platform permits writes to MSR::TEMPERATURE_TARGET:TCC_ACTIVE_OFFSET.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::PLATFORM_INFO:MAX_EFFICIENCY_RATIOThe minimum operating frequency of the processor.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::PERF_STATUS:FREQThe current operating frequency of the CPU.
Aggregation: average
Domain: cpu
Format: integer
Unit: hertz
MSR::TEMPERATURE_TARGET:PROCHOT_MINThe lowest temperature considered a high temperature. Measured temperatures at or above this value will generate a PROCHOT event.
Aggregation: expect_same
Domain: core
Format: integer
Unit: celsius
MSR::TEMPERATURE_TARGET:TCC_ACTIVE_OFFSETAn offset to subtract from MSR::TEMPERATURE_TARGET:PROCHOT_MIN as the cutoff to generate a PROCHOT event.
Aggregation: expect_same
Domain: core
Format: integer
Unit: celsius
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_0Maximum turbo frequency with up to MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_0 active cores.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_1Maximum turbo frequency with more than MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_0 and up to MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_1 active cores.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_2Maximum turbo frequency with more than MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_1 and up to MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_2 active cores.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_3Maximum turbo frequency with more than MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_2 and up to MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_3 active cores.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_4Maximum turbo frequency with more than MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_3 and up to MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_4 active cores.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_5Maximum turbo frequency with more than MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_4 and up to MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_5 active cores.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_6Maximum turbo frequency with more than MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_5 and up to MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_6 active cores.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_7Maximum turbo frequency with more than MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_6 and up to MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_7 active cores.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_0Maximum number of active cores for a maximum turbo frequency of MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_0.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_1Maximum number of active cores for a maximum turbo frequency of MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_1.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_2Maximum number of active cores for a maximum turbo frequency of MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_2.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_3Maximum number of active cores for a maximum turbo frequency of MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_3.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_4Maximum number of active cores for a maximum turbo frequency of MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_4.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_5Maximum number of active cores for a maximum turbo frequency of MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_5.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_6Maximum number of active cores for a maximum turbo frequency of MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_6.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::TURBO_RATIO_LIMIT_CORES:NUMCORE_7Maximum number of active cores for a maximum turbo frequency of MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_7.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::RAPL_POWER_UNIT:POWERThe resolution of RAPL power interfaces.
Aggregation: expect_same
Domain: package
Format: integer
Unit: watts
MSR::RAPL_POWER_UNIT:ENERGYThe resolution of RAPL energy interfaces.
Aggregation: expect_same
Domain: package
Format: integer
Unit: joules
MSR::RAPL_POWER_UNIT:TIMEThe resolution of RAPL time interfaces.
Aggregation: expect_same
Domain: package
Format: integer
Unit: seconds
MSR::PKG_POWER_LIMIT:LOCKIgnore any changes to PL1 and PL2 configuration in PKG_POWER_LIMIT until the next reset.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::PKG_ENERGY_STATUS:ENERGYAn increasing meter of energy consumed by the package over time. It will reset periodically due to roll-over.
Aggregation: sum
Domain: package
Format: integer
Unit: joules
MSR::PKG_POWER_INFO:THERMAL_SPEC_POWERMaximum power to stay within the thermal limits based on the design (TDP).
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_INFO:MIN_POWERThe minimum power limit based on the electrical specification.
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_INFO:MAX_POWERThe maximum power limit based on the electrical specification.
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_INFO:MAX_TIME_WINDOWThe maximum time accepted in MSR::PKG_POWER_LIMIT:PL1_TIME_WINDOW and MSR::PKG_POWER_LIMIT:PL2_TIME_WINDOW.
Aggregation: expect_same
Domain: package
Format: integer
Unit: seconds
MSR::DRAM_POWER_LIMIT:LOCKIgnore any changes to configuration in DRAM_POWER_LIMIT until the next reset.
Aggregation: expect_same
Domain: memory
Format: integer
Unit: none
MSR::DRAM_ENERGY_STATUS:ENERGYAn increasing meter of energy consumed by the DRAM over time. It will reset periodically due to roll-over.
Aggregation: sum
Domain: package
Format: integer
Unit: joules
MSR::DRAM_PERF_STATUS:THROTTLE_TIMEThe amount of time that the package was throttled below the requested frequency due to MSR::DRAM_POWER_LIMIT:POWER_LIMIT.
Aggregation: sum
Domain: memory
Format: integer
Unit: seconds
MSR::DRAM_POWER_INFO:THERMAL_SPEC_POWERMaximum DRAM power to stay within the thermal limits based on the design.
Aggregation: sum
Domain: memory
Format: integer
Unit: watts
MSR::DRAM_POWER_INFO:MIN_POWERThe minimum DRAM power limit based on the electrical specification.
Aggregation: sum
Domain: memory
Format: integer
Unit: watts
MSR::DRAM_POWER_INFO:MAX_POWERThe maximum DRAM power limit based on the electrical specification.
Aggregation: sum
Domain: memory
Format: integer
Unit: watts
MSR::DRAM_POWER_INFO:MAX_TIME_WINDOWThe maximum value accepted in MSR::DRAM_POWER_LIMIT:TIME_WINDOW.
Aggregation: expect_same
Domain: memory
Format: integer
Unit: seconds
MSR::PPERF:PCNTA filtered counter of MSR::APERF:ACNT that only increments for cycles the hardware expects are productive toward instruction execution. This counter cannot measure processor performance when the CPU is inactive.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::QM_CTR:RM_DATAThe raw counted value for the MSR::QM_EVTSEL:* configuration. Configurations that report bandwidth metrics report a raw value based on an implementation-specific counter. If reading a bandwidth metric, read the QM_CTR_SCALED alias instead.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::QM_CTR:UNAVAILABLEIndicates that no monitoring data is available, and MSR::QM_CTR:RM_DATA does not contain valid data. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::QM_CTR:ERRORIndicates an unsupported configuration in MSR::QM_EVTSEL:*, and that MSR::QM_CTR:RM_DATA does not contain valid data. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::UNCORE_PERF_STATUS:FREQThe current uncore frequency.
Aggregation: average
Domain: package
Format: integer
Unit: hertz
MSR::PM_ENABLE:HWP_ENABLEIndicates HWP enabled status. Once enabled a system reset is required to disable. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::HWP_CAPABILITIES:HIGHEST_PERFORMANCEMaximum non-guaranteed performance level when using HWP.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::HWP_CAPABILITIES:GUARANTEED_PERFORMANCECurrent guaranteed performance level. This may change dynamically based on various system constraints.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::HWP_CAPABILITIES:MOST_EFFICIENT_PERFORMANCECurrent value of the most efficient performance level. May change dynamically.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::HWP_CAPABILITIES:LOWEST_PERFORMANCEMinimum performance level when using HWP.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::HWP_REQUEST:DESIRED_PERFORMANCEAn explicit performance request. Setting to zero enables HWP Autonomous states. Any other value effectively disables HWP Autonomous selection.
Aggregation: average
Domain: cpu
Format: integer
Unit: hertz
MSR::HWP_REQUEST:ACTIVITY_WINDOWA hint to HWP indicating the observation window for performance/frequency optimizations.
Aggregation: average
Domain: cpu
Format: integer
Unit: none
MSR::CPU_SCALABILITY_RATIOMeasure of CPU Scalability as determined by the derivative of PCNT divided by the derivative of ACNT over 8 samples.
Aggregation: average
Domain: cpu
Format: double
Unit: none
Controls
Some MSR controls are available on specific miroarchitectures. Architectural controls are available across Intel x86 microarchitectures.
Architectural Controls
MSR::THERM_STATUS:THERMAL_STATUS_LOGIndicates whether the core’s on-die sensor has read a high temperature (PROCHOT) since the last time a zero was written to this control. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: core
Format: integer
Unit: none
MSR::THERM_STATUS:PROCHOT_LOGIndicates whether a high temperature (PROCHOT) or forced power reduction (FORCEPR) has been externally asserted since the last time a zero was written to this control. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: core
Format: integer
Unit: none
MSR::THERM_STATUS:CRITICAL_TEMP_LOGIndicates whether the core’s on-die sensor has read a critical temperature since the last time a zero was written to this control. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: core
Format: integer
Unit: none
MSR::THERM_STATUS:THERMAL_THRESH_1_LOGIndicates whether the core’s on-die sensor has read equal to or hotter than the threshold in MSR::THERM_INTERRUPT:THRESH_1 since the last time a zero was written to this control. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: core
Format: integer
Unit: none
MSR::THERM_STATUS:THERMAL_THRESH_2_LOGIndicates whether the core’s on-die sensor has read equal to or hotter than the threshold in MSR::THERM_INTERRUPT:THRESH_2 since the last time a zero was written to this control. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: core
Format: integer
Unit: none
MSR::THERM_STATUS:POWER_NOTIFICATION_LOGIndicates whether requested P-States or requested clock duty cycles were not met at some point since the last time a zero was written to this control. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: core
Format: integer
Unit: none
MSR::MISC_ENABLE:FAST_STRINGS_ENABLEEnable software control of the fast string feature for REP MOVS/STORS When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::MISC_ENABLE:ENHANCED_SPEEDSTEP_TECH_ENABLEEnable software control of P-States. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::MISC_ENABLE:TURBO_MODE_DISABLEIndicates whether opportunistic operating frequency above the processor’s base frequency is disabled. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PACKAGE_THERM_STATUS:THERMAL_STATUS_LOGIndicates whether the package’s on-die sensor has read a high temperature (PROCHOT) since the last time a zero was written to this control. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PACKAGE_THERM_STATUS:PROCHOT_LOGIndicates whether a package high temperature (PROCHOT) or forced power reduction (FORCEPR) has been externally asserted since the last time a zero was written to this control. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PACKAGE_THERM_STATUS:CRITICAL_TEMP_LOGIndicates whether the package’s on-die sensor has read a critical temperature since the last time a zero was written to this control. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PACKAGE_THERM_STATUS:THERMAL_THRESH_1_LOGIndicates whether the package’s on-die sensor has read equal to or hotter than the threshold in MSR::PACKAGE_THERM_INTERRUPT:THRESH_1 since the last time a zero was written to this control. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PACKAGE_THERM_STATUS:THERMAL_THRESH_2_LOGIndicates whether the package’s on-die sensor has read equal to or hotter than the threshold in MSR::PACKAGE_THERM_INTERRUPT:THRESH_2 since the last time a zero was written to this control. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PACKAGE_THERM_STATUS:POWER_NOTIFICATION_LOGIndicates whether requested P-States or requested clock duty cycles were not met due to a package power limit at some point since the last time a zero was written to this control. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL0:EVENT_SELECTSet an event code to select which event logic unit to monitor. This control combined with MSR::IA32_PERFEVTSEL0:UMASK defines which event to count. See https://download.01.org/perfmon for possible input values. Event counts are accumulated in MSR::IA32_PMC0:PERFCTR.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL0:UMASKSet a unit mask to select which event condition to monitor. This control combined with MSR::IA32_PERFEVTSEL0:EVENT_SELECT defines which event to count. See https://download.01.org/perfmon for possible input values. Event counts are accumulated in MSR::IA32_PMC0:PERFCTR.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL0:USRCount events while in user mode. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL0:OSCount events while in kernel mode. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL0:EDGEWhen set, count rising edges of the event signal instead of counting all instances where the event is observed. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL0:PCOnly applicable prior to the Sandy Bridge microarchitecture. When set, the processor’s PMi pins are toggled (on then off in back-to-back clock cycles) when an event is counted. When cleared, only event counter overflows toggle the PMi pins. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL0:INTIf set, generate an interrupt when the counter overflows. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL0:ANYTHREADIf set, increment event counts when the event occurs on any hardware thread from the configured thread’s core. Otherwise, only increment event counts when the configured thread triggers the event. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL0:ENEnable the counters selected in MSR::IA32_PERFEVTSEL0 if both this and MSR::PERF_GLOBAL_CTRL:EN_PMC0 are set. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL0:INVIndicates whether non-zero MSR::IA32_PERFEVTSEL0:CMASK events should be inverted. When the CMASK is inverted, increment the event count when the number of occurrences is less than the configured cutoff, instead of the default behavior of counting when the number of occurrences is greater than or equal to the cutoff. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL0:CMASKSet a mask for instances where multiple events are counted in a single clock cycle. When zero, all events are counted. When non-zero, a single event is counted when the number of event occurrences is greater or equal to the set CMASK value.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL1:EVENT_SELECTSet an event code to select which event logic unit to monitor. This control combined with MSR::IA32_PERFEVTSEL1:UMASK defines which event to count. See https://download.01.org/perfmon for possible input values. Event counts are accumulated in MSR::IA32_PMC1:PERFCTR.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL1:UMASKSet a unit mask to select which event condition to monitor. This control combined with MSR::IA32_PERFEVTSEL1:EVENT_SELECT defines which event to count. See https://download.01.org/perfmon for possible input values. Event counts are accumulated in MSR::IA32_PMC1:PERFCTR.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL1:USRCount events while in user mode. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL1:OSCount events while in kernel mode. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL1:EDGEWhen set, count rising edges of the event signal instead of counting all instances where the event is observed. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL1:PCOnly applicable prior to the Sandy Bridge microarchitecture. When set, the processor’s PMi pins are toggled (on then off in back-to-back clock cycles) when an event is counted. When cleared, only event counter overflows toggle the PMi pins. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL1:INTIf set, generate an interrupt when the counter overflows. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL1:ANYTHREADIf set, increment event counts when the event occurs on any hardware thread from the configured thread’s core. Otherwise, only increment event counts when the configured thread triggers the event. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL1:ENEnable the counters selected in MSR::IA32_PERFEVTSEL1 if both this and MSR::PERF_GLOBAL_CTRL:EN_PMC1 are set. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL1:INVIndicates whether non-zero MSR::IA32_PERFEVTSEL1:CMASK events should be inverted. When the CMASK is inverted, increment the event count when the number of occurrences is less than the configured cutoff, instead of the default behavior of counting when the number of occurrences is greater than or equal to the cutoff. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL1:CMASKSet a mask for instances where multiple events are counted in a single clock cycle. When zero, all events are counted. When non-zero, a single event is counted when the number of event occurrences is greater or equal to the set CMASK value.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL2:EVENT_SELECTSet an event code to select which event logic unit to monitor. This control combined with MSR::IA32_PERFEVTSEL2:UMASK defines which event to count. See https://download.01.org/perfmon for possible input values. Event counts are accumulated in MSR::IA32_PMC2:PERFCTR.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL2:UMASKSet a unit mask to select which event condition to monitor. This control combined with MSR::IA32_PERFEVTSEL2:EVENT_SELECT defines which event to count. See https://download.01.org/perfmon for possible input values. Event counts are accumulated in MSR::IA32_PMC2:PERFCTR.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL2:USRCount events while in user mode. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL2:OSCount events while in kernel mode. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL2:EDGEWhen set, count rising edges of the event signal instead of counting all instances where the event is observed. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL2:PCOnly applicable prior to the Sandy Bridge microarchitecture. When set, the processor’s PMi pins are toggled (on then off in back-to-back clock cycles) when an event is counted. When cleared, only event counter overflows toggle the PMi pins. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL2:INTIf set, generate an interrupt when the counter overflows. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL2:ANYTHREADIf set, increment event counts when the event occurs on any hardware thread from the configured thread’s core. Otherwise, only increment event counts when the configured thread triggers the event. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL2:ENEnable the counters selected in MSR::IA32_PERFEVTSEL2 if both this and MSR::PERF_GLOBAL_CTRL:EN_PMC2 are set. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL2:INVIndicates whether non-zero MSR::IA32_PERFEVTSEL2:CMASK events should be inverted. When the CMASK is inverted, increment the event count when the number of occurrences is less than the configured cutoff, instead of the default behavior of counting when the number of occurrences is greater than or equal to the cutoff. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL2:CMASKSet a mask for instances where multiple events are counted in a single clock cycle. When zero, all events are counted. When non-zero, a single event is counted when the number of event occurrences is greater or equal to the set CMASK value.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL3:EVENT_SELECTSet an event code to select which event logic unit to monitor. This control combined with MSR::IA32_PERFEVTSEL3:UMASK defines which event to count. See https://download.01.org/perfmon for possible input values. Event counts are accumulated in MSR::IA32_PMC3:PERFCTR.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL3:UMASKSet a unit mask to select which event condition to monitor. This control combined with MSR::IA32_PERFEVTSEL3:EVENT_SELECT defines which event to count. See https://download.01.org/perfmon for possible input values. Event counts are accumulated in MSR::IA32_PMC3:PERFCTR.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL3:USRCount events while in user mode. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL3:OSCount events while in kernel mode. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL3:EDGEWhen set, count rising edges of the event signal instead of counting all instances where the event is observed. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL3:PCOnly applicable prior to the Sandy Bridge microarchitecture. When set, the processor’s PMi pins are toggled (on then off in back-to-back clock cycles) when an event is counted. When cleared, only event counter overflows toggle the PMi pins. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL3:INTIf set, generate an interrupt when the counter overflows. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL3:ANYTHREADIf set, increment event counts when the event occurs on any hardware thread from the configured thread’s core. Otherwise, only increment event counts when the configured thread triggers the event. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL3:ENEnable the counters selected in MSR::IA32_PERFEVTSEL3 if both this and MSR::PERF_GLOBAL_CTRL:EN_PMC3 are set. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL3:INVIndicates whether non-zero MSR::IA32_PERFEVTSEL3:CMASK events should be inverted. When the CMASK is inverted, increment the event count when the number of occurrences is less than the configured cutoff, instead of the default behavior of counting when the number of occurrences is greater than or equal to the cutoff. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::IA32_PERFEVTSEL3:CMASKSet a mask for instances where multiple events are counted in a single clock cycle. When zero, all events are counted. When non-zero, a single event is counted when the number of event occurrences is greater or equal to the set CMASK value.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
MSR::FIXED_CTR_CTRL:EN0_OSCount MSR::FIXED_CTR0:INST_RETIRED_ANY events while in kernel mode. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::FIXED_CTR_CTRL:EN0_USRCount MSR::FIXED_CTR0:INST_RETIRED_ANY events while in user mode. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::FIXED_CTR_CTRL:EN0_PMIIf set, generate an interrupt when the MSR::FIXED_CTR0:INST_RETIRED_ANY counter overflows. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::FIXED_CTR_CTRL:EN1_OSCount MSR::FIXED_CTR1:CPU_CLK_UNHALTED_THREAD events while in kernel mode. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::FIXED_CTR_CTRL:EN1_USRCount MSR::FIXED_CTR1:CPU_CLK_UNHALTED_THREAD events while in user mode. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::FIXED_CTR_CTRL:EN1_PMIIf set, generate an interrupt when the MSR::FIXED_CTR1:CPU_CLK_UNHALTED_THREAD counter overflows. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::FIXED_CTR_CTRL:EN2_OSCount MSR::FIXED_CTR2:CPU_CLK_UNHALTED_REF_TSC events while in kernel mode. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::FIXED_CTR_CTRL:EN2_USRCount MSR::FIXED_CTR2:CPU_CLK_UNHALTED_REF_TSC events while in user mode. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::FIXED_CTR_CTRL:EN2_PMIIf set, generate an interrupt when the MSR::FIXED_CTR2:CPU_CLK_UNHALTED_REF_TSC counter overflows. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::PERF_GLOBAL_CTRL:EN_PMC0Enable programmable counter 0 if both this and MSR::IA32_PERFEVTSEL0:EN are set. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::PERF_GLOBAL_CTRL:EN_PMC1Enable programmable counter 1 if both this and MSR::IA32_PERFEVTSEL1:EN are set. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::PERF_GLOBAL_CTRL:EN_PMC2Enable programmable counter 2 if both this and MSR::IA32_PERFEVTSEL2:EN are set. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::PERF_GLOBAL_CTRL:EN_PMC3Enable programmable counter 3 if both this and MSR::IA32_PERFEVTSEL3:EN are set. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::PERF_GLOBAL_CTRL:EN_FIXED_CTR0Enable the MSR::FIXED_CTR0:INST_RETIRED_ANY counter. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::PERF_GLOBAL_CTRL:EN_FIXED_CTR1Enable the MSR::FIXED_CTR1:CPU_CLK_UNHALTED_THREAD counter. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::PERF_GLOBAL_CTRL:EN_FIXED_CTR2Enable the MSR::FIXED_CTR2:CPU_CLK_UNHALTED_REF_TSC counter. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::PERF_GLOBAL_OVF_CTRL:CLEAR_OVF_PMC0Write 1 to clear the global status bit for PMC0 overflow.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
MSR::PERF_GLOBAL_OVF_CTRL:CLEAR_OVF_PMC1Write 1 to clear the global status bit for PMC1 overflow.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
MSR::PERF_GLOBAL_OVF_CTRL:CLEAR_OVF_PMC2Write 1 to clear the global status bit for PMC2 overflow.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
MSR::PERF_GLOBAL_OVF_CTRL:CLEAR_OVF_PMC3Write 1 to clear the global status bit for PMC3 overflow.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
MSR::PERF_GLOBAL_OVF_CTRL:CLEAR_OVF_FIXED_CTR0Write 1 to clear the global status bit for MSR::FIXED_CTR0:INST_RETIRED_ANY overflow.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
MSR::PERF_GLOBAL_OVF_CTRL:CLEAR_OVF_FIXED_CTR1Write 1 to clear the global status bit for MSR::FIXED_CTR1:CPU_CLK_UNHALTED_THREAD overflow.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
MSR::PERF_GLOBAL_OVF_CTRL:CLEAR_OVF_FIXED_CTR2Write 1 to clear the global status bit for MSR::FIXED_CTR2:CPU_CLK_UNHALTED_REF_TSC overflow.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
Knights Landing (KNL) Controls
MSR::PERF_CTL:FREQTarget operating frequency of the CPU based on the control register. Note: when querying at a higher domain, if NaN is returned, query at its native domain.
Aggregation: average
Domain: package
Format: integer
Unit: hertz
MSR::PKG_POWER_LIMIT:PL1_POWER_LIMITThe average power usage limit over the time window specified in PL1_TIME_WINDOW.
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_LIMIT:PL1_LIMIT_ENABLEEnable the limit specified in PL1_POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PKG_POWER_LIMIT:PL1_CLAMP_ENABLEAllow processor cores to go below the requested P-State or T-State to achieve the requested PL1_POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PKG_POWER_LIMIT:PL1_TIME_WINDOWThe time window associated with power limit 1.
Aggregation: expect_same
Domain: package
Format: integer
Unit: seconds
MSR::PKG_POWER_LIMIT:PL2_POWER_LIMITThe average power usage limit over the time window specified in PL2_TIME_WINDOW.
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_LIMIT:PL2_LIMIT_ENABLEEnable the limit specified in PL2_POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PKG_POWER_LIMIT:PL2_CLAMP_ENABLEAllow processor cores to go below the requested P-State or T-State to achieve the requested PL2_POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PKG_POWER_LIMIT:PL2_TIME_WINDOWThe time window associated with power limit 2.
Aggregation: expect_same
Domain: package
Format: integer
Unit: seconds
MSR::DRAM_POWER_LIMIT:POWER_LIMITThe average DRAM power usage limit over the time window specified in TIME_WINDOW.
Aggregation: sum
Domain: memory
Format: integer
Unit: watts
MSR::DRAM_POWER_LIMIT:ENABLEEnable the limit specified in POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: memory
Format: integer
Unit: none
MSR::DRAM_POWER_LIMIT:TIME_WINDOWThe time window associated with the DRAM power limit.
Aggregation: expect_same
Domain: memory
Format: integer
Unit: seconds
MSR::UNCORE_RATIO_LIMIT:MIN_RATIOA lower limit for uncore frequency control. Note: when querying at a higher domain, if NaN is returned, query at its native domain.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::UNCORE_RATIO_LIMIT:MAX_RATIOAn upper limit for uncore frequency control. Note: when querying at a higher domain, if NaN is returned, query at its native domain.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
Sandy Bridge (SNB) Controls
MSR::PERF_CTL:FREQTarget operating frequency of the CPU based on the control register. Note: when querying at a higher domain, if NaN is returned, query at its native domain.
Aggregation: average
Domain: package
Format: integer
Unit: hertz
MSR::PKG_POWER_LIMIT:PL1_POWER_LIMITThe average power usage limit over the time window specified in PL1_TIME_WINDOW.
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_LIMIT:PL1_LIMIT_ENABLEEnable the limit specified in PL1_POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PKG_POWER_LIMIT:PL1_CLAMP_ENABLEAllow processor cores to go below the requested P-State or T-State to achieve the requested PL1_POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PKG_POWER_LIMIT:PL1_TIME_WINDOWThe time window associated with power limit 1.
Aggregation: expect_same
Domain: package
Format: integer
Unit: seconds
MSR::PKG_POWER_LIMIT:PL2_POWER_LIMITThe average power usage limit over the time window specified in PL2_TIME_WINDOW.
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_LIMIT:PL2_LIMIT_ENABLEEnable the limit specified in PL2_POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PKG_POWER_LIMIT:PL2_CLAMP_ENABLEAllow processor cores to go below the requested P-State or T-State to achieve the requested PL2_POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PKG_POWER_LIMIT:PL2_TIME_WINDOWThe time window associated with power limit 2.
Aggregation: expect_same
Domain: package
Format: integer
Unit: seconds
MSR::DRAM_POWER_LIMIT:POWER_LIMITThe average DRAM power usage limit over the time window specified in TIME_WINDOW.
Aggregation: sum
Domain: memory
Format: integer
Unit: watts
MSR::DRAM_POWER_LIMIT:ENABLEEnable the limit specified in POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: memory
Format: integer
Unit: none
MSR::DRAM_POWER_LIMIT:TIME_WINDOWThe time window associated with the DRAM power limit.
Aggregation: expect_same
Domain: memory
Format: integer
Unit: seconds
Haswell (HSX) Controls
MSR::PERF_CTL:FREQTarget operating frequency of the CPU based on the control register. Note: when querying at a higher domain, if NaN is returned, query at its native domain.
Aggregation: average
Domain: core
Format: integer
Unit: hertz
MSR::TURBO_RATIO_LIMIT2:PCU_SEMAPHOREIndicates whether MSR::TURBO_RATIO_LIMIT* settings are used instead of the the factory-set limits. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PKG_POWER_LIMIT:PL1_POWER_LIMITThe average power usage limit over the time window specified in PL1_TIME_WINDOW.
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_LIMIT:PL1_LIMIT_ENABLEEnable the limit specified in PL1_POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PKG_POWER_LIMIT:PL1_CLAMP_ENABLEAllow processor cores to go below the requested P-State or T-State to achieve the requested PL1_POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PKG_POWER_LIMIT:PL1_TIME_WINDOWThe time window associated with power limit 1.
Aggregation: expect_same
Domain: package
Format: integer
Unit: seconds
MSR::PKG_POWER_LIMIT:PL2_POWER_LIMITThe average power usage limit over the time window specified in PL2_TIME_WINDOW.
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_LIMIT:PL2_LIMIT_ENABLEEnable the limit specified in PL2_POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PKG_POWER_LIMIT:PL2_CLAMP_ENABLEAllow processor cores to go below the requested P-State or T-State to achieve the requested PL2_POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PKG_POWER_LIMIT:PL2_TIME_WINDOWThe time window associated with power limit 2.
Aggregation: expect_same
Domain: package
Format: integer
Unit: seconds
MSR::DRAM_POWER_LIMIT:POWER_LIMITThe average DRAM power usage limit over the time window specified in TIME_WINDOW.
Aggregation: sum
Domain: memory
Format: integer
Unit: watts
MSR::DRAM_POWER_LIMIT:ENABLEEnable the limit specified in POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: memory
Format: integer
Unit: none
MSR::DRAM_POWER_LIMIT:TIME_WINDOWThe time window associated with the DRAM power limit.
Aggregation: expect_same
Domain: memory
Format: integer
Unit: seconds
MSR::UNCORE_RATIO_LIMIT:MIN_RATIOA lower limit for uncore frequency control. Note: when querying at a higher domain, if NaN is returned, query at its native domain.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::UNCORE_RATIO_LIMIT:MAX_RATIOAn upper limit for uncore frequency control. Note: when querying at a higher domain, if NaN is returned, query at its native domain.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
Skylake (SKX) Controls
MSR::PERF_CTL:FREQTarget operating frequency of the CPU based on the control register. Note: when querying at a higher domain, if NaN is returned, query at its native domain.
Aggregation: average
Domain: core
Format: integer
Unit: hertz
MSR::PKG_POWER_LIMIT:PL1_POWER_LIMITThe average power usage limit over the time window specified in PL1_TIME_WINDOW.
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_LIMIT:PL1_LIMIT_ENABLEEnable the limit specified in PL1_POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PKG_POWER_LIMIT:PL1_CLAMP_ENABLEAllow processor cores to go below the requested P-State or T-State to achieve the requested PL1_POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PKG_POWER_LIMIT:PL1_TIME_WINDOWThe time window associated with power limit 1.
Aggregation: expect_same
Domain: package
Format: integer
Unit: seconds
MSR::PKG_POWER_LIMIT:PL2_POWER_LIMITThe average power usage limit over the time window specified in PL2_TIME_WINDOW.
Aggregation: sum
Domain: package
Format: integer
Unit: watts
MSR::PKG_POWER_LIMIT:PL2_LIMIT_ENABLEEnable the limit specified in PL2_POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PKG_POWER_LIMIT:PL2_CLAMP_ENABLEAllow processor cores to go below the requested P-State or T-State to achieve the requested PL2_POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: package
Format: integer
Unit: none
MSR::PKG_POWER_LIMIT:PL2_TIME_WINDOWThe time window associated with power limit 2.
Aggregation: expect_same
Domain: package
Format: integer
Unit: seconds
MSR::DRAM_POWER_LIMIT:POWER_LIMITThe average DRAM power usage limit over the time window specified in TIME_WINDOW.
Aggregation: sum
Domain: memory
Format: integer
Unit: watts
MSR::DRAM_POWER_LIMIT:ENABLEEnable the limit specified in POWER_LIMIT. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: memory
Format: integer
Unit: none
MSR::DRAM_POWER_LIMIT:TIME_WINDOWThe time window associated with the DRAM power limit.
Aggregation: expect_same
Domain: memory
Format: integer
Unit: seconds
MSR::UNCORE_RATIO_LIMIT:MIN_RATIOA lower limit for uncore frequency control. Note: when querying at a higher domain, if NaN is returned, query at its native domain.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::UNCORE_RATIO_LIMIT:MAX_RATIOAn upper limit for uncore frequency control. Note: when querying at a higher domain, if NaN is returned, query at its native domain.
Aggregation: expect_same
Domain: package
Format: integer
Unit: hertz
MSR::QM_EVTSEL:EVENT_IDSet an event code to choose which resource is monitored in MSR::QM_CTR:RM_DATA. Refer to the Intel(R) 64 and IA-32 Architectures Software Developer’s Manual for more information about how to use this MSR with Cache Monitoring Technology and Memory Bandwidth Monitoring. Event counts are accumulated in MSR::QM_CTR::RM_DATA.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::QM_EVTSEL:RMIDSpecify which resource monitoring identifier (RMID) must be active to update MSR::QM_CTR:RM_DATA. Associate RMIDs with CPUs by writing to MSR::PQR_ASSOC:RMID.
Aggregation: expect_same
Domain: package
Format: integer
Unit: none
MSR::PQR_ASSOC:RMIDThe resource monitoring identifier (RMID) currently associated with this CPU. Multiple CPUs are permitted to map to the same RMID. RMID-based resource monitoring interfaces track each monitored resource by a CPU package, RMID pair.
Aggregation: expect_same
Domain: cpu
Format: integer
Unit: none
MSR::MISC_FEATURE_CONTROL:L2_HW_PREFETCHER_DISABLEDisable for the L2 hardware prefetcher. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::MISC_FEATURE_CONTROL:L2_ADJACENT_PREFETCHER_DISABLEDisable for the L2 adjacent cache line prefetcher When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::MISC_FEATURE_CONTROL:DCU_HW_PREFETCHER_DISABLEDisable for the L1 data cache prefetcher When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::MISC_FEATURE_CONTROL:DCU_IP_PREFETCHER_DISABLEDisable for the L1 data cache instruction pointer prefetcher When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::HWP_REQUEST:MINIMUM_PERFORMANCEA hint to HWP on the minimum performance level required.
Aggregation: average
Domain: cpu
Format: integer
Unit: hertz
MSR::HWP_REQUEST:MAXIMUM_PERFORMANCEA hint to HWP on the maximum performance level required.
Aggregation: average
Domain: cpu
Format: integer
Unit: hertz
MSR::HWP_REQUEST:ENERGY_PERFORMANCE_PREFERENCEInfluences rate of performance increase/decrease. 0x00 = performance, 0xFF = energy efficiency.
Aggregation: average
Domain: cpu
Format: integer
Unit: none
MSR::HWP_REQUEST:PACKAGE_CONTROLIf set overrides requests with the package level request. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::HWP_REQUEST:EPP_VALIDIf set indicates HWP should use the related cpu MSR field value regardless of the PACKAGE_CONTROL bit setting. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::HWP_REQUEST:DESIRED_VALIDIf set indicates HWP should use the related cpu MSR field value regardless of the PACKAGE_CONTROL bit setting. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::HWP_REQUEST:MAXIMUM_VALIDIf set indicates HWP should use the related cpu MSR field value regardless of the PACKAGE_CONTROL bit setting. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::HWP_REQUEST:MINIMUM_VALIDIf set indicates HWP should use the related cpu MSR field value regardless of the PACKAGE_CONTROL bit setting. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::HWP_STATUS:GUARANTEED_PERFORMANCE_CHANGELog bit indicating if a GUARANTEED_PERFORMANCE change has occurred. Software responsible to clear via write to 0. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::HWP_STATUS:EXCURSION_TO_MINIMUMLog bit indicating if an excursion below the minimum requested performance has occurred. Software responsible to clear via write to 0. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::HWP_STATUS:HIGHEST_CHANGELog bit indicating if a HIGHEST_PEROFRMANCE change has occurred. Software responsible to clear via write to 0. When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::HWP_STATUS:PECI_OVERRIDE_ENTRYIndicates a PECI override request that will override the HWP MSR values has started. Software responsible to clear via write to 0 When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
MSR::HWP_STATUS:PECI_OVERRIDE_EXITIndicates a PECI override request that will override the HWP MSR values has ended. Software responsible to clear via write to 0 When reading at a higher level domain than its native domain, it aggregates as the count of all such bits that have been set.
Aggregation: sum
Domain: cpu
Format: integer
Unit: none
Aliases
This IOGroup provides the following high-level aliases:
Signal Aliases
BOARD_ENERGYMaps to
MSR::PLATFORM_ENERGY_STATUS:ENERGYBOARD_POWERMaps to
MSR::BOARD_POWERBOARD_POWER_LIMIT_CONTROLMaps to
MSR::PLATFORM_POWER_LIMIT:PL1_POWER_LIMITBOARD_POWER_TIME_WINDOW_CONTROLMaps to
MSR::PLATFORM_POWER_LIMIT:PL1_TIME_WINDOWCPU_CORE_TEMPERATUREMaps to
MSR::THERM_STATUS:DIGITAL_READOUTCPU_CYCLES_REFERENCEMaps to
MSR::FIXED_CTR2:CPU_CLK_UNHALTED_REF_TSCCPU_CYCLES_THREADMaps to
MSR::FIXED_CTR1:CPU_CLK_UNHALTED_THREADCPU_ENERGYMaps to
MSR::PKG_ENERGY_STATUS:ENERGYCPU_FREQUENCY_MAX_CONTROLMaps to
MSR::HWP_REQUEST:MAXIMUM_PERFORMANCEor toMSR::PERF_CTL:FREQif HWP is disabled.CPU_FREQUENCY_MAX_AVAILMaps to
MSR::TURBO_RATIO_LIMIT:MAX_RATIO_LIMIT_0CPU_FREQUENCY_MIN_CONTROLMaps to
MSR::HWP_REQUEST:MINIMUM_PERFORMANCE. Not exposed if HWP is disabled.CPU_FREQUENCY_STATUSMaps to
MSR::PERF_STATUS:FREQCPU_INSTRUCTIONS_RETIREDMaps to
MSR::FIXED_CTR0:INST_RETIRED_ANYCPU_PACKAGE_TEMPERATUREMaps to
MSR::PACKAGE_THERM_STATUS:DIGITAL_READOUTCPU_POWERAverage package power over 40 ms or 8 control loop iterations.
CPU_POWER_LIMIT_CONTROLMaps to
MSR::PKG_POWER_LIMIT:PL1_POWER_LIMITCPU_POWER_MAX_AVAILMaps to
MSR::PKG_POWER_INFO:MAX_POWERCPU_POWER_MIN_AVAILMaps to
MSR::PKG_POWER_INFO:MIN_POWERCPU_POWER_LIMIT_DEFAULTMaps to
MSR::PKG_POWER_INFO:THERMAL_SPEC_POWERCPU_POWER_TIME_WINDOW_CONTROLMaps to
MSR::PKG_POWER_LIMIT:PL1_TIME_WINDOWCPU_TIMESTAMP_COUNTERMaps to
MSR::TIME_STAMP_COUNTER:TIMESTAMP_COUNTCPU_UNCORE_FREQUENCY_MAX_CONTROLMaps to
MSR::UNCORE_RATIO_LIMIT:MAX_RATIOCPU_UNCORE_FREQUENCY_MIN_CONTROLMaps to
MSR::UNCORE_RATIO_LIMIT:MIN_RATIOCPU_UNCORE_FREQUENCY_STATUSMaps to
MSR::UNCORE_PERF_STATUS:FREQDRAM_ENERGYMaps to
MSR::DRAM_ENERGY_STATUS:ENERGYDRAM_POWERAverage DRAM power over 40 ms or 8 control loop iterations.
MSR::BOARD_ENERGYMaps to
MSR::PLATFORM_ENERGY_STATUS:ENERGYMSR::BOARD_POWERAverage board power over 40 ms or 8 control loop iterations. Derived from
MSR::BOARD_ENERGYMSR::QM_CTR_SCALEDMaps to
MSR::QM_CTR:RM_DATA, scaled by the processor’s counter resolution for bandwidth accounting in bytes.MSR::QM_CTR_SCALED_RATEMaps to the rate of change in
MSR::QM_CTR_SCALED.
Control Aliases
CPU_FREQUENCY_DESIRED_CONTROLMaps to
MSR::HWP_REQUEST:DESIRED_PERFORMANCECPU_FREQUENCY_MAX_CONTROLMaps to
MSR::HWP_REQUEST:MAXIMUM_PERFORMANCEor toMSR::PERF_CTL:FREQif HWP is disabledCPU_FREQUENCY_MIN_CONTROLMaps to
MSR::HWP_REQUEST:MINIMUM_PERFORMANCE. Not exposed if HWP is disabled.CPU_POWER_LIMIT_CONTROLMaps to
MSR::PKG_POWER_LIMIT:PL1_POWER_LIMITCPU_POWER_TIME_WINDOW_CONTROLMaps to
MSR::PKG_POWER_LIMIT:PL1_TIME_WINDOWCPU_UNCORE_FREQUENCY_MAX_CONTROLMaps to
MSR::UNCORE_RATIO_LIMIT:MAX_RATIOCPU_UNCORE_FREQUENCY_MIN_CONTROLMaps to
MSR::UNCORE_RATIO_LIMIT:MIN_RATIO
Example
The following example uses geopmread and geopmwrite command-line tools. These steps can also be followed within an agent.
Setting Frequency
Set target operating frequency:
geopmwrite CPU_FREQUENCY_MAX_CONTROL core 0 1700000000
Read setting and current operating frequency:
geopmread CPU_FREQUENCY_MAX_CONTROL core 0
geopmread CPU_FREQUENCY_STATUS core 0
Setting A Power Limit
Set power limit
geopmwrite CPU_POWER_LIMIT_CONTROL package 0 20
Read setting and current power
geopmread CPU_POWER_LIMIT_CONTROL package 0
geopmread CPU_POWER package 0
See Also
geopm_pio(7), geopm(7), geopm::IOGroup(3), geopmwrite(1), geopmread(1)